gui_start


read_file -format verilog {/home/weijj19/weijj19/PDK/OA/library/demo-updown-cnt.v}

set_operating_conditions -library scadv10_cln65gp_rvt_tt_1p0v_25c tt_1p0v_25c

set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports clk]]
set all_in_ex_clk_rstn [remove_from_collection $all_in_ex_clk [get_ports rstn]]
set_driving_cell -lib_cell INVX11BA10TR -library scadv10_cln65gp_rvt_tt_1p0v_25c $all_in_ex_clk_rstn

set_fanout_load 2 [all_outputs]
set_wire_load_model -name tsmc65_wl10 -library scadv10_cln65gp_rvt_tt_1p0v_25c

create_clock -name "clk" -period 10 -waveform { 0.000 5  }  { clk  }
set_dont_touch_network  [ find clock clk ]

set_input_delay -max 4 -clock clk $all_in_ex_clk_rstn
set_output_delay -max 4 -clock clk [all_outputs]

compile -exact_map

uplevel #0 { report_timing -path full -delay max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group }
uplevel #0 { report_area -nosplit }

write -hierarchy -format ddc
write -hierarchy -format verilog -output /home/weijj19/weijj19/PDK/OA/library/demo-updown-cnt-post.v
write_sdf demo-updown-cnt.sdf
write_sdc demo-updown-cnt.sdc

quit
